This specification relates to using neural networks for electronic design automation and, more specifically, for generating a computer chip floorplan.
Computer chip floorplans are schematic representations of the placement of some or all of the circuits of a computer chip on the surface, i.e., the chip area, of the computer chip.
Neural networks are machine learning models that employ one or more layers of nonlinear units to predict an output for a received input. Some neural networks include one or more hidden layers in addition to an output layer. The output of each hidden layer is used as input to the next layer in the network, i.e., the next hidden layer or the output layer. Each layer of the network generates an output from received inputs in accordance with current values of a respective set of parameters.